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msm54c865 ? semiconductor 1/44 description the msm54c865 is a 512kbit cmos multiport dram composed of a 65,536-word by 8-bit dynamic ram and a 256-word by 8-bit sam. its ram and sam operate independently and asynchronously. the msm54c865 supports three types of operaton: random access to ram port, high speed serial access to sam port and bidirectional transfer of data between any selected row in the ram port and the sam port. in addition to the conventional multiport dram operating modes, the msm54c865 features the block write and flash write functions on the ram port and a split data transfer capability on the sam port. the sam port requires no refresh operation because it uses static cmos flip-flops. features ? single power supply: 5 v 10% ? full ttl compatibility ? multiport organization ram : 64k word 8 bits sam : 256 word 8 bits ? fast page mode ? write per bit ? masked flash write ? masked block write ? ras only refresh ? cas before ras refresh ? hidden refresh ? serial read/write ? 256 tap location ? bidirectional data transfer ? split transfer ? masked write transfer ? refresh :256 cycles/4 ms ? package options: 40-pin 475 mil plastic zip (zip40-p-475-1.27) (product : msm54c865-xxzs) 40-pin 400 mil plastic soj (soj40-p-400-1.27) (product : msm54c865-xxjs) xx indicates speed rank. product family ? semiconductor msm54c865 65,536-word 8-bit multiport dram family MSM54C865-70 msm54c865-80 msm54c865-10 access time ram sam 70 ns 25 ns 80 ns 25 ns 100 ns 25 ns cycle time ram sam 140 ns 30 ns 150 ns 30 ns 180 ns 30 ns power dissipation operating 120 ma 110 ma 100 ma standby 8 ma 8 ma 8 ma e2l0011-17-y1 this version: jan. 1998 previous version: dec. 1996
msm54c865 ? semiconductor 2/44 pin configuration (top view) w6/io6 w8/io8 sio5 sio7 v ss1 sio1 sio3 dt / oe w2/io2 v ss3 v cc1 ras a6 nc a4 v cc2 a3 a1 qsf dsf sc sio1 sio2 sio3 sio4 dt / oe w1/io1 w2/io2 w3/io3 w4/io4 v cc1 wb / we nc ras nc nc a6 a5 a4 v cc2 v ss1 sio8 sio7 sio6 sio5 se w8/io8 w7/io7 w6/io6 w5/io5 v ss2 dsf nc cas qsf a0 a1 a2 a3 a7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 40-pin plastic soj 40-pin plastic zip w5/io5 w7/io7 se sio6 sio8 sc sio2 sio4 w1/io1 w3/io3 w4/io4 wb / we nc v ss2 a5 nc a7 a2 a0 cas pin name a0 - a7 w1/io1 - w8/io8 sio1 - sio8 ras cas wb / we dt / oe function address input ram inputs/outputs sam inputs/outputs row address strobe column address strobe write per bit/write enable transfer/output enable pin name sc se dsf qsf v cc v ss nc function serial clock sam port enable special function input special function output power supply (5 v) ground (0 v) no connection note : the same power supply voltage must be provided to every v cc pin, and the same gnd voltage level must be provided to every v ss pin.
msm54c865 ? semiconductor 3/44 block diagram column address buffer row address buffer refresh counter a0 - a7 sam address buffer sam address counter row decoder column decoder sense amp. 256 256 8 ram array gate sam gate sam sio1 - sio8 qsf serial decoder block write control i/o control flash write control sam input buffer sam output buffer column mask register color register mask register ram input buffer ram output buffer timing generator ras cas dt / oe wb / we dsf sc se v cc v ss w1/io1 - w8/io8
msm54c865 ? semiconductor 4/44 electrical characteristics absolute maximum ratings parameter input output voltage output current power dissipation operating temperature storage temperature symbol v t i os p d t opr t stg condition ta = 25c ta = 25c ta = 25c rating C1.0 to 7.0 50 1 0 to 70 C55 to 150 unit v ma w c c (note: 16) recommended operating conditions parameter power supply voltage input high voltage input low voltage symbol v cc v ih v il min. 4.5 2.4 C1.0 unit v v v (ta = 0c to 70c) (note: 17) typ. 5.0 max. 5.5 6.5 0.8 capacitance parameter input capacitance input/output capacitance output capacitance symbol c i c i/o c o (qsf) min. unit pf pf pf (v cc = 5 v 10%, f = 1 mhz, ta = 25c) max. 7 9 9 note: this parameter is periodically sampled and is not 100% tested. dc characteristics 1 parameter output "h" level voltage output "l" level voltage input leakage current output leakage current symbol v oh v ol i li i lo condition i oh = C2 ma i ol = 2 ma 0 v in v cc 0 v out 5.5 v min. 2.4 C10 C10 unit v m a all other pins not output disable max. 0.4 10 10 under test = 0 v
msm54c865 ? semiconductor 5/44 dc characteristics 2 -70 -80 -10 unit note symbol item (ram) sam max. max. max. 85 75 65 ma 1, 2 i cc1 operating current standby 120 110 100 1, 2 ( ras , cas cycling, t rc = t rc min.) active 888 standby current 50 45 40 1, 2 ( ras , cas = v ih ) 85 75 65 1, 2 ras only refresh current 120 110 100 1, 2 ( ras cycling, cas = v ih , t rc = t rc min.) 70 65 60 1, 2 page mode current 120 110 100 1, 2 ( ras = v il , cas cycling, t pc = t pc min.) 85 75 65 1, 2 cas before ras refresh current 120 110 100 1, 2 ( ras cycling, cas before ras , t rc = t rc min.) 85 75 65 1, 2 data transfer current 120 110 100 1, 2 ( ras , cas cycling, t rc = t rc min.) 85 75 65 1, 2 flash write current 120 110 100 1, 2 ( ras , cas cycling, t rc = t rc min.) 85 75 65 1, 2 block write current 120 110 100 1, 2 ( ras , cas cycling, t rc = t rc min.) i cc1a i cc2 i cc2a i cc3 i cc3a i cc4 i cc4a i cc5 i cc5a i cc6 i cc6a i cc7 i cc7a i cc8 i cc8a standby active standby active standby active standby active standby active standby active standby active (v cc = 5 v 10%, ta = 0c to 70c) 3
msm54c865 ? semiconductor 6/44 ac characteristics (1/3) parameter symbol note unit ns 180 150 140 ns 55 40 35 ns 25 25 20 ns 50 45 40 ns 35 3 35 3 35 3 ns 100k 100 100k 80 100k 70 t rc t prwc t aa t cac t cpa t rasp t cas t rcd max. min. max. min. max. min. -10 -80 -70 ns 100 90 90 ns 10k 25 10k 25 10k 20 13 20 20 20 ns 55 50 45 t pc t rac ns 100 80 70 9 ns 20 0 20 0 20 0 t off ns 70 60 60 ns 25 25 20 t rsh ns 100 80 70 t csh t t t rp ns 10k 100 10k 80 10k 70 t ras t rad 13 20 15 15 t asr 0 0 0 t rah 10 10 10 t asc 0 0 0 t cah 15 15 15 t ar 70 55 55 t rcs 0 0 0 t rch 10 0 0 0 t rrh 10 0 0 0 t wch 15 15 15 t wcr 70 55 55 t wp 15 15 15 t rwl 25 20 20 t cwl 25 20 20 7, 13 7, 14 7, 14 7, 13 6 ns 75 55 50 ns 50 40 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 235 195 195 t rwc t ral t crp ns 55 40 35 10 10 10 t cp 10 10 10 ns ns access time from column address column address hold time referenced to ras column address set-up time row address set-up time access time from cas column address hold time cas pulse width cas precharge time (fast page mode) access time from cas precharge cas to ras precharge time cas hold time write command to cas lead time output buffer turn-off delay fast page mode cycle time fast page mode read modify write cycle time row address hold time ras pulse width (fast page mode only) random read or write cycle time ras to cas delay time read command hold time read command set-up time read modify write cycle time ras precharge time read command hold time referenced to ras write command to ras lead time access time from ras ras to column address delay time column address to ras lead time ras pulse width ras hold time transition time (rise and fall) write command hold time referenced to ras write command pulse width write command hold time t cpn 10 10 10 ns cas precharge time (v cc = 5 v 10%, ta = 0c to 70c) note 4, 5, 6
msm54c865 ? semiconductor 7/44 parameter symbol note unit ns 55 45 45 ns 0 0 0 ns 0 0 0 ns 20 0 10 0 10 0 ns 10 10 10 t rwd t cwd t dzc t dzo t csr t ref t wsr max. min. max. min. max. min. -10 -80 -70 ns 130 100 100 ms 4 4 4 0 0 0 t awd ns 80 65 65 ns 25 20 20 t oea ns 20 10 10 ns 10 10 10 t chr ns 0 0 0 t rpc t oez t oeh ns 15 15 15 t roh t rwh 15 15 15 t ms 0 0 0 t mh 15 15 15 t ths 0 0 0 t thh 15 15 15 t tls 0 0 0 t tlh 15 15 15 12 12 ns ns ns ns ns ns ns ns 10k 10k 10k t rth 80 65 60 ns 10k 10k 10k t ath 30 30 25 ns t cth 25 25 20 ns t esr t reh ns 0 0 0 15 15 15 ns 12 column address to we delay time cas hold time for cas before ras cycle cas set-up time for cas before ras cycle cas to we delay time data to cas delay time data to oe delay time se set-up time referenced to ras write per bit mask data hold time write per bit mask data set-up time oe command hold time refresh period se hold time referenced to ras ras hold time referenced to oe ras precharge to cas active time ras to we delay time wb hold time access time from oe wb set-up time output buffer turn-off delay from oe dt low hold time referenced to column address (real time read transfer) dt low hold time referenced to cas (real time read transfer) dt high hold time dt high set-up time dt low hold time dt low set-up time dt low hold time referenced to ras (real time read transfer) ns 0 0 0 t ds ns 70 55 55 t dhr ns 15 15 15 t dh 11 11 data hold time data hold time referenced to ras data set-up time t wcs 0 0 0ns write command set-up time 12 ns 20 10 10 t oed oe to data delay time (v cc = 5 v 10%, ta = 0c to 70c) note 4, 5, 6 9 7 t fsr 0 0 0 ns dsf set-up time referenced to ras t rfh 15 15 15 ns dsf hold time referenced to ras (1) t fhr 70 55 55 ns dsf hold time referenced to ras (2) t fsc 0 0 0 ns dsf set-up time referenced to cas t cfh 15 15 15 ns dsf hold time referenced to cas ac characteristics (2/3)
msm54c865 ? semiconductor 8/44 parameter symbol note unit ns 10 10 10 ns 25 25 25 ns 5 5 5 ns 25 25 25 t scc t scp t sca t soh max. min. max. min. max. min. -10 -80 -70 ns 30 30 30 t sc ns 10 10 10 8 ns 25 25 25 t sea ns 25 25 25 t se t sep ns 20 0 20 0 20 0 t sez t srd t sze 0 0 0 t szs 0 0 0 t sws 5 5 5 t swh 15 15 15 t swis 5 5 5 t swih 15 15 15 8 9 ns ns ns ns ns ns ns t sdd ns 50 40 40 access time from sc sc pulse width (sc high time) sc cycle time sc precharge time (sc low time) ras to serial input delay time se pulse width access time from se se precharge time serial write disable hold time serial write disable set-up time serial write enable set-up time serial input to se delay time serial input to first sc delay time serial output buffer turn-off delay from se serial output hold time from sc serial write enable hold time 25 20 20 ras to first sc delay time (serial input) ns 15 15 15 t tsd ns 50 10 40 10 40 10 t sdz ns 30 25 25 t srs 9 serial output buffer turn-off delay from ras (pseudo write transfer) dt to first sc delay time (read transfer) last sc to ras set-up time (serial input) (v cc = 5 v 10%, ta = 0c to 70c) note 4, 5, 6 t sds 0 0 0 t sdh 15 15 15 ns ns serial input hold time serial input set-up time t trp 70 60 60 t tp 30 20 20 t rsd 100 80 70 t asd 50 45 45 t csd 25 25 20 t tsl 5 5 5 ns ns ns ns ns ns column address to first sc delay time (read transfer) ras to first sc delay time (read transfer) dt to ras precharge time last sc to dt lead time (real time read transfer) dt precharge time cas to first sc delay time (read transfer) t sts 30 30 25 ns split transfer set-up time t sth 30 30 25 ns split transfer hold time t sqd ns sc-qsf delay time 25 25 25 t tqd ns dt -qsf delay time t cqd ns cas -qsf delay time t rqd ns ras -qsf delay time 25 25 25 35 35 35 85 75 75 ac characteristics (3/3)
msm54c865 ? semiconductor 9/44 notes: 1. these parameters depend on output loading. specified values are obtained with the output open. 2. these parameters are masured at minimum cycle test. 3. i cc2 (max.) are mesured under the condition of ttl input level. 4. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . 5. an initial pause of 200 m s is required after power-up followed by any 8 ras cycles ( dt / oe high) and any 8 sc cycles before proper divice operation is achieved. in the case of using an internal refresh counter, a minimum of 8 cas before ras initialization cycles in stead of 8 ras cycles are required. 6. ac measurements assume t t = 5 ns. 7. ram port outputs are mesured with a load equivalent to 1 ttl load and 100 pf. output reference levels are v oh /v ol = 2.4 v/1.0 v. 8. sam port outputs are measured with a load equivalent to 1 ttl load and 30 pf. output reference levels are v oh /v ol = 2.0 v/1.0 v. 9. t off (max.), t oez (max.), t sdz (max.) and t sez (max.) difine the time at which the outputs achieve the open circuit condition and are not reference to output voltage levels. 10. either t rch or t rrh must be satisfied for a read cycle. 11. these parameters are referenced to cas leading edge of early write cycles and to wb / we leading edge in oe controlled write cycles and read modify write cycles. 12. t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the cycle is an early write cycle, and the data out pin will remain open circuit (high impedance) throughout the entire cycle : if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.) and t awd 3 t awd (min.) the cycle is a read-write cycle and the data out will contain data read from the selected cell : if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indterminate. 13. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only : if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 14. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only : if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 15. input levels at the ac parameter measurement are 3.0 v/0 v. 16. stresses greater than those listed under absolute maximum ratings may cause permenent damege to the device. 17. all voltages are referenced to v ss .
msm54c865 ? semiconductor 10/44 timing waveform read cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf in out w1/io1 - w8/io8 v ih v il C C v ih v il e e v ih v il e e v ih v il e e v ih v il e e v ih v il e e v ih v il e e v oh v ol e e t rc t ras t rp t ar t csh t crp t rcd t rsh t cpn t cas t rad t ral t asr t rah t asc t cah row address column address t rcs t rch t rrh t roh t ths t thh t fsr t rfh t fhr t fsc t cfh t oea t dzo t cac t aa t rac t off t oez open valid data-out
msm54c865 ? semiconductor 11/44 write cycle (early write) "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf in out w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rc t ras t rp t ar t csh t crp t rcd t rsh t cas t cpn t rad t ral t asr t rah t asc t cah row address column address t wsr t rwh t wcs t wch t wp t wcr t cwl t rwl t ths t thh t fhr t fsr t rfh t fsc t cfh t ms t mh t ds t dh wm1 data valid data-in t dhr open *1 *1 wb / we 0 1 w1/io1 - w8/io8 wm1 data dont care cycle write per bit normal write wm1 data: 0: write disable 1: write enable
msm54c865 ? semiconductor 12/44 write cycle ( oe control) "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf in out w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rc t ras t rp t ar t csh t crp t rcd t rsh t cpn t cas t rad t ral t asr t rah t asc t cah row address column address t cwl t rwl t wp t wsr t rwh *1 t wcr t oeh t ths t fhr t fsr t rfh t fsc t cfh t ms t mh t ds t dh wm1 data valid data-in t dhr open *1 wb / we 0 1 w1/io1 - w8/io8 wm1 data dont care cycle write per bit normal write wm1 data: 0: write disable 1: write enable
msm54c865 ? semiconductor 13/44 read modify write cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf in out w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rwc t ras t rp t ar t csh t crp t rcd t rsh t cpn t rad t asr t rah t asc t cah row address column address t wsr t rwh t rcs t cwd t cwl t rwl t wp *1 t awd t rwd t ths t thh t oeh t fhr t fsr t rfh t fsc t cfh t dzc t ms t mh t dzo t oed t ds t dh wm1 data valid data-in t oea t cac t aa t rac t oez open valid data-out t cas *1 wb / we 0 1 w1/io1 - w8/io8 wm1 data dont care cycle write per bit normal write wm1 data: 0: write disable 1: write enable
msm54c865 ? semiconductor 14/44 fast page mode read cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf in out w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rasp t rp t ar t pc t crp t rcd t cas t cp t cas t cp t rsh t cas t cpn t rad t csh t asr t rah t asc t cah t asc t cah t ral t asc t cah row address column address 1 column address 2 column address n t rcs t rch t rcs t rch t rcs t rch t rrh t ths t thh t fsc t fsr t thh t cfh t fsc t cfh t fsc t cfh t fhr t dzo t cpa t cpa t oea t cac t aa t rac t off t oez t oea t cac t aa t off t oez t oea t cac t aa t off t oez open data-out 1 data-out 2 data-out n
msm54c865 ? semiconductor 15/44 fast page mode write cycle (early write) "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf in out w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rasp t rp t ar t pc t crp t rcd t cas t cp t cas t cp t cas t rsh t cpn t rad t csh t asr t rah t asc t cah t asc t cah t asc t ral t cah row address column address 1 column address 2 column address n t wcr t wsr t rwh t wcs t wch t wp t wcs t wch t wp t wcs t wch t wp t ths t thh t cwl t cwl t cwl t rwl t fhr t rfh t fsr t fsc t cfh t fsc t cfh t fsc t cfh t mh t ms t ds t dh t ds t dh t ds t dh t dhr wm1 data data-in 1 data-in 2 data-in n open *1 *1 wb / we 0 1 w1/io1 - w8/io8 wm1 data dont care cycle write per bit normal write wm1 data: 0: write disable 1: write enable
msm54c865 ? semiconductor 16/44 fast page mode read modify write cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf in out w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rasp t rp t ar t csh t prwc t rsh t rcd t cas t cp t cas t cp t cas t asc t asr t rah t cah t cwl t asc t cah t cwl t asc t cah t cwl t rwl row address column address 1 column address 2 column address n t rwh t wsr t wp t wp t wp *1 t cwd t cwd t cwd t rwd t ths t thh t rfh t fhr t fsr t fsc t fsc t fsc t cfh t cfh t cfh t mh t ms t dzo t dzc t ds t oed t dh t dzo t dzc t oed t ds t dh t dzo t dzc t ds t oed t dh wm1 data data- in 1 data- in 2 data- in n t oea t cac t aa t rac t oez t oea t cac t aa t oez t oea t cac t oez t aa data- out 1 data- out 2 data- out n *1 wb / we 0 1 w1/io1 - w8/io8 wm1 data dont care cycle write per bit normal write wm1 data: 0: write disable 1: write enable
msm54c865 ? semiconductor 17/44 ras only refresh cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol e e t rc t ras t rp t crp t rpc t crp t asr t rah row address t ths t thh t fsr t rfh open
msm54c865 ? semiconductor 18/44 cas before ras refresh cycle "h" or "l" ras cas wb / we dt / oe dsf w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rp t rc t rp t ras t rpc t csr t cpn t chr t off open note: a0 - a7 = don't care ("h" or "l")
msm54c865 ? semiconductor 19/44 hidden refresh cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rc t rc t ras t ar t rp t ras t rp t crp t rcd t rsh t chr t cpn t rad t ral t asr t rah t asc t cah row address column address t rcs t rrh t wsr t rwh t ths t thh t roh t fsr t rfh t fsc t cfh t fhr t oez t off t oea t cac t aa t off t oez valid data-out
msm54c865 ? semiconductor 20/44 load color register cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf in out w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rc t ras t rp t crp t csh t rcd t rsh t cas t cpn t asr t rah row address t wsr t rwh t cwl t rwl t wp t wcr t ths t wch t oeh t fsr t rfh t dhr t ds t dh t ds t dh color data-in (delayed write) color data-in (early write)
msm54c865 ? semiconductor 21/44 read color register cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol e e w1/io1 - w8/io8 t rc t ras t rp t csh t crp t rcd t rsh t cas t cpn t asr t rah row address t ths t thh t roh t rrh t rch t wsr t rwh t rcs t fsr t rfh t oea t cac t off t oez t rac valid data-out
msm54c865 ? semiconductor 22/44 flash write cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf in out w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rc t ras t rp t csh t crp t rcd t rsh t cpn t cas t asr t rah row address t wsr t rwh t tls t tlh t fsr t rfh t ms t mh wm1 data open wm1 data 0 1 cycle flash write disable flash write enable
msm54c865 ? semiconductor 23/44 block write cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf in out w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rc t ras t rp t ar t csh t crp t rcd t rsh t cas t cpn t rad t ral t asr t rah t asc t cah row address column address (a2c - a7c) t wsr t rwh *1 t ths t thh t fhr t fsr t rfh t fsc t cfh t ms t mh t ds t dh t dhr *2 *3 open *1 wb / we 0 1 *2 w1/io1 - w8/io8 wm1 data dont care cycle masked block write block write (non mask) wm1 data: 0: write disable 1: write enable *3) column select w1/io1 C column 0 (a1c = 0, a0c = 0) w2/io2 C column 1 (a1c = 0, a0c = 1) w3/io3 C column 2 (a1c = 1, a0c = 0) w4/io4 C column 3 (a1c = 1, a0c = 1) wn/ion = 0 : disable = 1 : enable
msm54c865 ? semiconductor 24/44 fast page mode block write cycle "h" or "l" ras cas a0 - a7 dt / oe wb / we dsf v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il e e w1/io1 - w8/io8 t rasp t rp t ar t crp t csh t rcd t pc t cas t cp t pc t rsh t cas t cp t cas t cpn t rad t rah t asr t asc t cah t asc t cah t asc t cah t ral row address a2c - a7c a2c - a7c a2c - a7c t ths t thh t wsr t rwh *1 t fhr t fsr t mh t rfh t fsc t cfh t fsc t cfh t fsc t cfh t dhr t ms t ds t dh t ds t dh t ds t dh *2 *3 *3 *3 *1 wb / we 0 1 *2 w1/io1 - w8/io8 wm1 data dont care cycle masked block write block write (non mask) wm1 data: 0: write disable 1: write enable *3) column select w1/io1 C column 0 (a1c = 0, a0c = 0) w2/io2 C column 1 (a1c = 0, a0c = 1) w3/io3 C column 2 (a1c = 1, a0c = 0) w4/io4 C column 3 (a1c = 1, a0c = 1) wn/ion = 0 : disable = 1 : enable
msm54c865 ? semiconductor 25/44 read transfer cycle (previous transfer is write transfer cycle) "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C w1/io1 - w8/io8 v oh v ol e e sc v ih v il e e in v ih v il e e out v oh v ol e e sio1 - sio8 qsf v oh v ol e e t rc t ras t rp t ar t csh t crp t rcd t rsh t cpn t cas t asr t rah t rad t asc t cah t ral row address sam start address a0 - a7: tap t wsr t rwh t trp t tls t tlh t tp t fsr t rfh t asd t off t rsd t csd t srs t sc t tsd t scc t scp t sc t scp inhibit rising transient t sds t sdh t szs valid data-in t cqd t tqd t sca t soh valid data-out t rqd tap msb (a7) note: se = v il
msm54c865 ? semiconductor 26/44 real time read transfer cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C w1/io1 - w8/io8 v oh v ol C C sc v ih v il C C in v ih v il C C out v oh v ol C C sio1 - sio8 qsf v oh v ol C C note: se = v il t rc t ras t rp t ar t csh t crp t rcd t rsh t cas t cpn t rad t asr t rah t asc t cah t ral row address sam start address a0 - a7: tap t wsr t rwh t ath t cth t trp t tls t rth t tp t fsr t rfh t off t scc t sc t scp t tsl t tsd t sca t soh t tqd open t sca t soh valid data-out valid data-out valid data-out valid data-out valid data-out previous row data new row data tap msb (a7)
msm54c865 ? semiconductor 27/44 split read transfer cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C sc v ih v il C C qsf v oh v ol C C note: se = v il ............... ............... v oh v ol e e sio1 - sio8 t rc t ras t rp t ar t crp t csh t rcd t rsh t cpn t cas t rad t ral t asr t rah t asc t cah row address sam start address (n) a0 - a6: tap t wsr t rwh t tls t tlh t sts t rfh t sth t fsr 255 (127) n (n+128) n+1 (n+129) n+2 (n+130) 125 (253) 126 (254) n+128 (n) 127 (255) t sqd 254 (126) 255 (127) n (n+128) n+1 (n+129) n+2 (n+130) 125 (253) 126 (254) 127 (255) t sqd lower sam 0 to 127 upper sam 128 to 255
msm54c865 ? semiconductor 28/44 pseudo write transfer cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C sc v ih v il C C qsf v oh v ol C C sio1 - sio8 v oh v ol e e w1/io1 - w8/io8 v oh v ol e e out in v ih v il e e se v ih v il C C t rc t ras t rp t ar t csh t crp t rcd t rsh t cas t cpn t asr t rah t rad t asc t ral t cah row address sam start address a0 - a7: tap t wsr t rwh t tls t tlh t fsr t rfh t off open t srd t scc t scp t sc t scp t srs inhibit rising transient t sc t esr t reh t sws t sdd t sdz t sez t sds t sdh valid data-in t sca valid data-out valid data-out open t soh t rqd t cqd tap msb (a7) serial output data serial input data
msm54c865 ? semiconductor 29/44 write transfer cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C sc v ih v il C C qsf v oh v ol C C sio1 ~ sio8 v oh v ol C C w1/io1 - w8/io8 v oh v ol C C out in v ih v il C C se v ih v il C C t rc t ras t rp t ar t crp t csh t rcd t rsh t cas t cpn t rad t asr t rah t asc t ral t cah row address sam start address a0 - a7: tap t wsr t rwh t tls t tlh t fsr t rfh t ms t off t mh wm1 data open t srd t scc t scp t sc t scp t srs inhibit rising transient t sc t esr t reh t sws t sds t sdh valid data-in t cqd t sds t sdh valid data-in valid data-in t rqd open tap msb (a7) previous row data new row data wm1 data: 0: transfer disable 1: transfer enable
msm54c865 ? semiconductor 30/44 split write transfer cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe dsf v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C sc v ih v il C C qsf v oh v ol C C note: se = v il sio1 - sio8 v oh v ol C C w1/io1 - w8/io8 v ih v il C C ............... ............... t rc t ras t rp t ar t csh t crp t rcd t rsh t cpn t cas t rad t ral t asr t rah t asc t cah row address sam start address (n) a0 - a6: tap t wsr t rwh t tls t tlh t sts t rfh t sth t fsr t ms t off t mh open wm1 data t sqd t sqd 255 (127) n (n+128) n+1 (n+129) n+2 (n+130) 125 (253) 126 (254) n+128 (n) 127 (255) 255 (127) n (n+128) n+1 (n+129) n+2 (n+130) 125 (253) 126 (254) n+128 (n) 127 (255) lower sam 0 to 127 upper sam 128 to 255
msm54c865 ? semiconductor 31/44 serial read cycle ( se = v il ) serial read cycle ( se controlled outputs) "h" or "l" ras dt / oe v ih v il C C v ih v il C C sc v ih v il C C note: se = v il v oh v ol e e sio1 - sio8 t ths t thh t scc t scc t scc t scc t scc t sc t sc t sc t sc t sc t scp t scp t scp t scp t scp t scp t sca t sca t sca t sca t sca t soh t soh t soh t soh t soh valid data-out valid data-out valid data-out valid data-out valid data-out valid data-out "h" or "l" ras dt / oe v ih v il C C v ih v il C C sc v ih v il C C se v ih v il C C in out v ih v il C C v oh v ol C C sio1 - sio8 t ths t thh t scc t scc t scc t scc t scc t sc t sc t sc t sc t sc t scp t scp t scp t scp t scp t scp t sep t sze t sca t soh t sez t sea t sca t sca t soh t sca t soh open valid data-out valid data-out valid data-out valid data-out valid data-out
msm54c865 ? semiconductor 32/44 serial write cycle ( se = v il ) serial write cycle ( se controlled inputs) "h" or "l" ras dt / oe v ih v il C C v ih v il C C sc v ih v il C C note: se = v il v ih v il e e sio1 - sio8 t ths t thh t scc t scc t scc t scc t scc t sc t sc t sc t sc t sc t sdh t sdh t sdh t sdh t sdh t scp t scp t scp t scp t scp t scp t sds t sds t sds t sds t sds valid data-in valid data-in valid data-in valid data-in valid data-in "h" or "l" ras dt / oe v ih v il C C v ih v il C C sc v ih v il C C in out v ih v il C C v oh v ol C C sio1 - sio8 v ih v il C C se t ths t thh t scc t scc t scc t scc t scc t sc t sc t sc t sc t sc t scp t scp t scp t scp t scp t scp t swih t swih t sws t swh t sep t sws t swh t sep t sws t swh t swis t se t sds t sdh t sds t sdh t se t swis t se t sds t sdh valid data-in valid data-in valid data-in open
msm54c865 ? semiconductor 33/44 pin function address input : a0 - a7 the 16 address bits decode an 8-bit location of the 525,288 locations in the msm54c865-js/zs memory array. the address bits are multiplexed to 8 address input pins (a0 to a7) as standard dram. 8 row address bits are latched at the falling edge of ras . the following 8 column address bits are latched at the falling edge of cas . row address strobe : ras ras is a basic ram control signal. the ram port is in standby mode when the ras level is "high". as the standard dram's ras signal function, ras is control input that latches the row address bits and random access cycle begins at the falling edge of ras . in addition to the conventional ras signal function, the level of the input signals, cas , dt / oe , wb / we , dsf, and se , at the falling edge of ras , determines the msm54c865-js/zs operation modes. column address strobe : cas as the standard dram's cas signal function, cas is the control signal that latches the column address input and the states of the special function input dsf to select, in conjunction with the ras control, either read/write operations or the special block write feature on the ram port when the dsf is held "low" at the falling edge of ras . cas also acts as a ram port output enable signal. data transfer/out enable : dt / oe dt / oe is also a control input signal having multiple functions. as the standard dram's oe signal function, dt / oe is used as an output enable control when dt / oe is "high" at the falling edge of ras . in addition to the conventional oe signal function, a data transfer operation is started between the ram port and the sam port when dt / oe is "low" at the falling edge of ras . write per bit/ write enable : wb / we wb / we is also a control input signal having multiple functions. as the standard dram's we signal function, it is used to write data into the memory on the ram port when wb / we is "high" at the falling edge of ras . in addition to the conventional we signal function, the wb / we determines the write-per-bit function when wb / we is "low" at the falling edge of ras , during ram port operations. the wb / we is "high" at the falling edge of ras , the data is transferred from ram to sam (read transfer). when wb / we is "low" at the falling edge of ras , the data is transferred sam to ram (write transfer).
msm54c865 ? semiconductor 34/44 write mask data/data input and output : w1/io1 - w8/io8 w1/io1 - w8/io8 have the functions of both input/output and a control input signal. as the standard dram's i/o pins, input data on the w1/io1 - w8/io8 are written into the ram port during the write cycle. the input data is latched at the falling edge of either cas or wb / we , whichever occurs later. the ram data out buffers, which will output read data from ras , cas , dt / oe and column address are satisfied and the output data will remain valid as long as cas and dt / oe are kept "low". the outputs will return to the high impedance state at the rising edge of either cas or dt / oe , whichever occurs earlier. in addition to the conventional i/o function, the w1/io1 - w8/io8 have the function to set the mask data, which select mask input pins out of eight input pins, w1/io1 - w8/io8, at the falling edge of ras . data is written to the dram on data lines where the write-mask data is a logic "1". the write-mask data is valid for only one cycle. serial clock : sc sc is a main serial cycle control input signal. all operation of sam port are synchronized with the serial clock sc. data is shifted in or out of the sam registers at the rising edge of sc. in a serial read , the output data becomes valid on the sio pins after the maximum specified serial access time t sca from the rising edge of sc. the sc also increments the 8 bits serial pointer which is used to select the sam address. the pointer address is incremented in a wrap-around mode to select sequential locations after the setting location which is determined by the column address in the read transfer cycle. when the pointer reaches the most significant address location (decimal 255), the next sc clock will place it at the least significant address location (decimal 0). the sc must be held data constant v ih or v il level during read/pseudo write/write-transfer operations and should not be clocked while the sam port is in the standby mode to prevent the sam pointer from being incremented. serial enable : se the se is a serial access enable control and serial read/write control signal. in a serial read cycle, se is used as an output control. in a serial write cycle, se is used as a write enable control. when se is "high", serial access is disable, however, the serial address pointer location is still incremented when sc is clocked even when se is "high". special function input : dsf the dsf is latched at the falling edge of ras and cas and allows for the selection of several ram port and transfer operating modes. in addition to the conventional multiport dram, the special function consisting of flash write, block write, load/read color register and split read/ write transfer can be invoked. special function output : qsf qsf is an output signal which, during split register mode, indicates which half of the split sam is being accessed. qsf "low" indicates that the lower split sam (0-127) is being accessed. qsf 'high" indicates that the upper sam (128-255) is being accessed. qsf is monitored so that after it toggles and after allowing for a delay of t sts , split read/write transfer operation can be performed on the non-active sam.
msm54c865 ? semiconductor 35/44 serial input/output : sio1 - sio8 serial input/output mode is determined by the most recent read, write or pseudo write transfer cycle. when a read transfer cycle is performed, the sam port is in the output mode. when a write or pseudo write transfer cycle is performed, the sam port is switched from output mode to input mode.
msm54c865 ? semiconductor 36/44 operation modes table-1 shows the function truth table for a listing of all available ram ports and transfer operation of msm54c865. the ram port and data transfer operations are determined by the state of cas , dt / oe , wb / we , se and dsf at the falling edge of ras and by the level of dsf at the falling edge of cas . table-1. function truth table ras cas dt / oe wb / we dsf se cas dsf address ras cas w/io ras cas cas / we write mask register wm color function 0* *** 10 000 10 001 10 01* 10 10* 10 11* 11 00* 11 00* 11 01* 11 10* 11 10* 11 11* * * * * * 0 1 * 0 1 * * row row row row row row row row row row row tap tap tap tap tap column * column * * wm1 * wm1 * * wm1 wm1 wm1 * * * * * * * * * * * * din * din color wm1 wm1 wm1 wm1 wm1 use use use load c.b.r refresh masked write transfer pseudo write transfer split write transfer read transfer split read transfer write per bit masked block write masked flash write read write block write load color register column a2c-7c column select column a2c-7c column select load use load use load use load use load use if the dsf is 'high" at the falling edge of ras , special functions such as split transfer, flash write, and load/read color register can be invoked. if the dsf is "low" at the falling edge of ras and "high" at the falling edge of cas , the block write feature can be invoked. if the dsf is "low" at the falling edge of ras and cas , only the conventional multiport dram operating feature can be invoked.
msm54c865 ? semiconductor 37/44 ram port operation fast page mode fast page mode allows data to be transferred into or out of multiple column locations of the same row by performing multiple cas cycle during a single activity for a period up to 100 m seconds. for the initial fast page mode access, the output data is valid after the specified access times from ras , cas , column address and dt / oe . for all subsequent fast page mode read operations, the output data is valid after the specified access times from cas , column address and dt / oe . when the write-per-bit function is enabled, the mask data latched at the falling edge of ras is maintained throughout the fast page mode write or read or read modify write cycle. ras -only refresh the data in the dram requires periodic refreshing to prevent data loss. refreshing is accomplished by performing a memory cycle at each of the 256 rows in the dram array within the specified 4 ms refresh period. although any normal memory cycle will perform the refresh operation, this function is most easily accomplished with " ras -only" cycle. block write block write allows for the data in the color register to be written into 4 consecutive column address locations starting from a selectively controlled on an i/o basis and column mask capability is also available. block write cycle is performed by holding cas , dt / oe "high" and dsf "low" at the falling edge of ras and by holding dsf "high" at the falling edge of cas . the state of the wb / we input at the falling edge of ras determines whether or not the i/o data mask is enabled ( wb / we must be "low" to enable the i/o mask or "high" to disable mask). at the falling edge of ras , a valid row address and i/o mask data are also specified. at the falling edge of cas , the starting column address location and column mask data must be provided. during a block write cycle, the 2 least significant column address locations (a0c, a1c) are internally controlled and only the 6 most significant column addresses (a2c - a7c) are latched at the falling edge of cas .
msm54c865 ? semiconductor 38/44 sam port operation single register mode high speed serial read or write operation can be performed through the sam port independent of the ram port operation, except during read/write transfer cycles. the preceding transfer operation determines the direction of data flow through the sam port. if the preceding transfer is a read transfer, the sam port is in the output made. if the preceding transfer is write or pseudo write transfer, the sam port is in the input mode. the pseudo write transfer only switches the sam port from output mode to input mode (data is not transffered from sam port to ram port). serial data can be read out of the sam after a read transfer has been performed. the data is shifted out of the sam starting at any of the 256 bits locations. the tap location corresponds to the column address selected at the falling edge of cas during the read or write transfer cycle. the sam register is configured as a circular data register. the data is shifted out sequentially starting from the selected tap location to the most significant bit (255) and then wraps around the least significant bit (0). split register mode in split register mode, data can be shifted into or out of one half of the sam while a split read or split write transfer is being performed on the other half of the sam. conventional (non split) read, write, or pseudo write transfer cycle must precede any split read or split write transfers. the split read and write transfers will not change the sam port mode set by preceding conventional transfer operation. in the split register mode, serial data can be shifted in or out of one of the split sam registers starting from any at the 128 tap locations, excluding the last address of each split sam. data is shifted in or out sequentially starting from the selected tap location to the most significant bit (127 or 255) of the first split sam. then the sam pointer moves to the tap location selected for the second split sam to shift data in or out sequentially starting from this tap location to the most significant bit (255 or 127) and finally wraps around to the least significant bit. 0 1 2 127 128 255 tap tap 129
msm54c865 ? semiconductor 39/44 data transfer operation the msm54c865 features two types of bidirectional data transfer capability between ram and sam, as shown in figure 1 below. 1) conventional (non split) transfer : 256 words by 8 bits of data can be loaded from ram to sam (read transfer) or from sam to ram (write transfer). 2) split transfer : 128 words by 8 bits of data can be loaded from the lower/upper half of the ram to the lower/upper half of the sam (split read transfer) or from the lower/upper half of sam to the lower/upper half of ram (split write transfer). the conventional transfer and split transfer modes are controlled by the dsf input signal. 256 256 8 memory array 256 8 256 128 8 memory array 128 8 256 128 8 memory array 128 8 1) conventional transfer 2) split transfer figure 1. the msm54c865 supports five types of transfer operation : read transfer, split read transfer, write transfer, pseudo write transfer and split write transfer as shown in truth table. data transfer is invoked by holding the dt / oe signal "low" at the falling edge of ras . the type of transfer operation is determined by the state of cas , wb / we , se and dsf latched at the falling edge of ras . during conventional transfer operations, the sam port is switched from input to output mode (read transfer) or output to input mode (write/pseudo write transfer) whereas it remains unchanged during split transfer operation (split read transfer or split write transfer).
msm54c865 ? semiconductor 40/44 read transfer operation read transfer consists of loading a selected row of data from the ram into the sam register. a read transfer is invoked by holding cas "high" , dt / oe "low", wb / we "high", and dsf "low" at the falling edge of ras . the low address selected at the falling edge of ras determines the ram row to be transferred into the sam. the transfer cycle is completed at the rising edge of dt / oe . when the transfer is completed, the sam port is set into the output mode. in a read/real time read transfer cycle, the transfer of a new row of data is completed at the rising edge of dt / oe and this data becomes valid on the sio lines after the specified access time t sca from the rising edge of the subsequent sc cycles. the start address of the serial pointer of the sam is determined by the column address selected at the falling edge of cas . in a read transfer cycle (which is preceded by a write transfer cycle), sc clock must be held at a constant v il or v ih , after the sc high time has been satisfied. a rising edge of the sc clock must not occur until after the specified delay t tsd from the rising edge of dt / oe . in a real time transfer cycle ( which is preceded by another read transfer cycle), the previous row data appears on the sio lines until the dt / oe signal goes "high" and the serial access time t sca for the following serial clock is satisfied. this feature allows for the first bit of the new row of data to appear on the serial output as soon as the last bit of the previous row has been strobed without any timing loss. to make this continuous data flow possible, the rising edge of dt / oe must be synchronized with ras , cas and the subsequent rising edge of sc (t rth , t cth , and t tsl / t tsd must be satisfied). write transfer operation write transfer cycle consists of loading the content of the sam register into a selected row of the ram. if the sam data to be transferred must first be loaded through the sam, a pseudo write transfer operation must precede the write transfer cycles. a write transfer is invoked by holding cas "high", dt / oe "low", wb / we "low", se "low" and dsf "low" at the falling edge of ras . this write transfer is selectively controlled per ram i/o block by setting the mask data on the wi/ oi lines at the falling edge of ras . the row address selected at the falling edge of ras determines the ram row address into which the data will be transferred. the column address selected at the falling edge of cas determines the start address of the serial pointer of the sam. after the write transfer is completed, the sio lines are set in the input mode so that serial data synchronized with the sc clock can be loaded. when consecutive write transfer operations are performed, new data must not be written into the serial register until the ras cycle of the preceding write transfer is completed. consequently, the sc clock must be held at a constant v il or v ih during the ras cycle. a rising edge of the sc clock is only allowed after the specified delay t srd from the rising edge of ras , at which time a new row of data can be written in the serial register. pseudo write transfer operation pseudo write transfer cycle must be performed before loading data into the serial register after a read transfer operation has been executed. the only purpose of a pseudo write transfer is to change sam port mode from output mode to input mode (a data transfer from sam to ram does not occur). after the serial register is loaded with new data, a write transfer is invoked by holding cas "high", dt / oe "low", wb / we "low", se "high" and dsf "low" at the falling edge of ras . the timing conditions are the same as the one for the write transfer cycle except for the state of se at the falling edge of ras .
msm54c865 ? semiconductor 41/44 split data transfer and qsf the msm54c865 features a bidirectional split data transfer capability between the ram and sam. during split data transfer operation, the serial register is split into two halves which can be controlled independently. split read or split write transfer operation can be performed to or from one half of the serial register while serial data can be shifted into or out of the other half of the serial register. the most significant column address location (a7c) is controlled internally to determine which half of the serial register will be reloaded from the ram. qsf is an output which indicates which half of the serial register is in an active state. qsf changes state when the last sc clock is applied to active split sam. split read transfer operation split read transfer consists of loading 128 words by 8 bits of data from a selected row of the split ram into the corresponding non-active split sam register. serial data can be shifted out from of the other half of the split sam register simultaneously. during split read transfer operation, the ram port input clocks do not have to be synchronized with the serial clock sc, thus eliminating timing restrictions as in the case of real time read transfers. a split read transfer can be performed after a delay of t sts , from the change of state of the qsf output, is satisfied. conventional (non-split) read transfer operation must be preceded by split read transfer cycles. split write transfer operation split write transfer consists of loading 128 words by 8 bits of data from the non-active split sam register into a selected row of the corresponding split ram. serial data can be shifted into the other half of the split sam register simultaneously. during split write transfer operation, the ram port input clocks do not have to be synchronized with the serial clock sc, thus allowing for real time transfer. a split write transfer can be performed after a delay of t sts , from the change of state of the qsf output, is satisfied. a pseudo write transfer operation must precede split write transfer. the purpose of the pseudo write transfer operation is to switch the sam port from output mode to input mode and to set the initial tap location prior to split write transfer operation. transfer operation without cas during all transfer cycles, the cas input clock must be cycled, so that the column addresses are latched at the falling edge of cas , to set the sam tap location. tap location in split transfer 1) in a split transfer operation, column address a0c through a6c must be latched at the falling edge of cas in order to set the tap location in one of the split sam registers. during a split transfer, column address a7c is controlled internally and therefore it is ignored internally at the falling edge of cas . during a split transfer, it is not permissible to set the last address location (a0c-a6c = 7f), in either the lower sam or the upper sam, as the tap location.
msm54c865 ? semiconductor 42/44 power-up power must be applied to the ras and dt / oe input signals to pull them "high" before or at the same time as the v cc supply is turned on. after power-up, a pause of 200 m s minimum is required with ras and dt / oe held "high". after the pause, a minimum of 8 ras and 8 sc dummy cycles must be performed to stabilize the internal circuitry, before valid read, write or transfer operations can begin. during the initialization period, the dt / oe signal must be held "high". if the internal refresh counter is used, a minimum 8 cas before ras cycles are required instead of 8 ras cycles.
msm54c865 ? semiconductor 43/44 (unit : mm) package dimensions zip40-p-475-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 3.46 typ. mirror finish
msm54c865 ? semiconductor 44/44 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). soj40-p-400-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.70 typ. mirror finish

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